module name (input a, output b); ... endmodule | Basic module |
module name #(parameter N=8) (input [N-1:0] a); | Parameterized module |
input wire [7:0] data; | 8-bit input |
output reg [7:0] result; | 8-bit registered output |
inout [7:0] bidir; | Bidirectional port |
wire [7:0] w; | Wire (combinational) |
reg [7:0] r; | Register |
integer i; | Integer (32-bit) |
parameter N = 8; | Compile-time constant |
localparam M = N*2; | Local parameter |
reg [7:0] mem [0:255]; | 256x8 memory array |
&, |, ^, ~ | Bitwise AND, OR, XOR, NOT |
&&, ||, ! | Logical AND, OR, NOT |
==, !=, ===, !== | Equality (=== includes x,z) |
<, <=, >, >= | Comparison |
>>, <<, >>>, <<< | Shift (>>> arithmetic) |
? : | Ternary conditional |
{a, b} | Concatenation |
{4{a}} | Replication (4 copies) |
assign y = a & b; | Combinational logic |
assign y = sel ? a : b; | Mux with ternary |
assign #10 y = a; | With delay |
always @(posedge clk) | Rising edge triggered |
always @(negedge clk) | Falling edge triggered |
always @(posedge clk or negedge rst_n) | Async reset |
always @(*) | Combinational (all inputs) |
always_ff @(posedge clk) | SV: Sequential |
always_comb | SV: Combinational |
if (cond) ... else ... | If-else |
case (sel) 2'b00: ... default: ... endcase | Case statement |
casez (sel) | Case with z as don't care |
casex (sel) | Case with x,z as don't care |
for (i=0; i<8; i=i+1) | For loop |
while (cond) ... | While loop |
generate for ... endgenerate | Generate block |
always @(posedge clk) if (rst) q <= 0; else q <= d; | D flip-flop with sync reset |
always @(posedge clk or negedge rst_n) if (!rst_n) q <= 0; else q <= d; | D FF with async reset |
always @(posedge clk) if (en) q <= d; | D FF with enable |
always @(posedge clk) cnt <= cnt + 1; | Counter |
assign mux_out = sel ? a : b; | 2:1 Mux |
assign dec = 1 << sel; | Decoder |
dff u1 (.clk(clk), .d(d), .q(q)); | Named port connection |
dff u1 (clk, d, q); | Positional connection |
dff #(.WIDTH(8)) u1 (...); | Parameter override |
dff u1 (.clk, .d, .q); | SV: Implicit port |
entity name is port (...); end name; | Entity declaration |
architecture rtl of name is ... begin ... end rtl; | Architecture |
port (clk : in std_logic; q : out std_logic); | Port declaration |
generic (N : integer := 8); | Generic parameter |
std_logic : ('0','1','X','Z',...) | Single bit |
std_logic_vector(7 downto 0) | 8-bit vector |
unsigned(7 downto 0) | Unsigned arithmetic |
signed(7 downto 0) | Signed arithmetic |
integer range 0 to 255 | Integer with range |
type state_t is (IDLE, RUN, DONE); | Enumeration type |
constant N : integer := 8; | Constant |
and, or, xor, not, nand, nor | Logical operators |
=, /=, <, <=, >, >= | Comparison |
+, -, *, /, mod, rem | Arithmetic |
sll, srl, sla, sra, rol, ror | Shift/rotate |
& | Concatenation |
y <= a and b; | Signal assignment |
y <= a when sel='1' else b; | Conditional assignment |
with sel select y <= a when "00", b when others; | Selected assignment |
process (clk) begin if rising_edge(clk) then ... end if; end process; | Clocked process |
process (all) begin ... end process; | Combinational (VHDL-2008) |
if rst = '1' then ... elsif rising_edge(clk) then ... | Async reset |
if cond then ... elsif cond then ... else ... end if; | If statement |
case sel is when "00" => ... when others => ... end case; | Case statement |
for i in 0 to 7 loop ... end loop; | For loop |
while cond loop ... end loop; | While loop |
initial begin ... end | Initial block |
#10; | Delay 10 time units |
@(posedge clk); | Wait for clock edge |
always #5 clk = ~clk; | Clock generator |
$display("msg %d", var); | Print message |
$monitor("a=%b b=%b", a, b); | Monitor signals |
$finish; | End simulation |
$dumpfile("wave.vcd"); $dumpvars; | Waveform dump |
clk <= not clk after 5 ns; | Clock generator |
wait for 10 ns; | Wait for time |
wait until rising_edge(clk); | Wait for clock |
report "message" severity note; | Print message |
assert cond report "error" severity failure; | Assertion |