set target_library "lib.db" | Set target library |
set link_library "* lib.db" | Set link library |
set search_path ". ./lib" | Set search path |
read_verilog design.v | Read Verilog |
read_vhdl design.vhd | Read VHDL |
read_ddc design.ddc | Read DDC format |
analyze -format verilog file.v | Analyze design |
elaborate top_module | Elaborate design |
current_design top_module | Set current design |
link | Link design |
create_clock -period 10 [get_ports clk] | Define clock (10ns) |
create_generated_clock -divide_by 2 -source clk [get_pins div/Q] | Generated clock |
set_clock_uncertainty 0.1 [get_clocks clk] | Clock uncertainty |
set_input_delay -clock clk 2 [get_ports data_in] | Input delay |
set_output_delay -clock clk 2 [get_ports data_out] | Output delay |
set_max_delay 5 -from [get_ports a] -to [get_ports b] | Max delay constraint |
set_false_path -from [get_clocks clk1] -to [get_clocks clk2] | False path |
set_multicycle_path 2 -setup -from [get_pins reg/Q] | Multicycle path |
compile | Basic compile |
compile_ultra | High-effort compile |
compile_ultra -area_high_effort_script | Area optimization |
compile_ultra -timing_high_effort_script | Timing optimization |
set_max_area 0 | Minimize area |
set_max_dynamic_power 0 | Minimize power |
report_timing | Timing report |
report_timing -delay_type max -max_paths 10 | Detailed timing |
report_area | Area report |
report_power | Power report |
report_constraint -all_violators | Constraint violations |
report_qor | Quality of results |
write -format verilog -output netlist.v | Write netlist |
write -format ddc -output design.ddc | Write DDC |
write_sdc constraints.sdc | Write SDC |
read_verilog netlist.v | Read netlist |
read_db lib.db | Read library |
read_sdc constraints.sdc | Read SDC constraints |
read_parasitics design.spef | Read SPEF parasitics |
link_design top_module | Link design |
update_timing | Update timing |
report_timing | Report timing |
report_timing -from [get_pins reg1/Q] -to [get_pins reg2/D] | Path timing |
report_timing -delay_type min | Hold timing |
report_timing -delay_type max | Setup timing |
report_clock_timing -type summary | Clock summary |
report_analysis_coverage | Analysis coverage |
get_timing_paths -nworst 100 | Get worst paths |
set_operating_conditions -min bc -max wc | Operating conditions |
report_si_bottleneck | Signal integrity |
report_noise | Noise analysis |
report_power | Power analysis |
vcs design.v testbench.v -o simv | Compile design |
vcs -sverilog design.sv | SystemVerilog compile |
vcs -debug_all | Enable debug |
vcs +v2k | Verilog-2001 mode |
vcs -f filelist.f | Read file list |
vcs +define+DEBUG | Define macro |
vcs +incdir+./include | Include directory |
./simv | Run simulation |
./simv +vcs+finish+1000 | Run with timeout |
./simv +ntb_random_seed=12345 | Set random seed |
./simv -gui | Run with DVE GUI |
./simv -ucli | Interactive mode |
vcs -cm line+cond+fsm+branch | Enable coverage |
./simv -cm line+cond | Collect coverage |
urg -dir simv.vdb | Generate coverage report |
$fsdbDumpfile("wave.fsdb"); | FSDB dump (in code) |
$fsdbDumpvars; | Dump all signals |
dve -vpd vcdplus.vpd | Open waveform in DVE |
create_lib -technology tech.tf library_name | Create library |
read_verilog netlist.v | Read netlist |
read_sdc constraints.sdc | Read constraints |
initialize_floorplan -core_utilization 0.7 | Initialize floorplan |
create_placement -floorplan | Initial placement |
legalize_placement | Legalize placement |
create_power_straps | Create power grid |
place_opt | Placement optimization |
clock_opt | Clock tree synthesis |
route_auto | Auto routing |
route_opt | Route optimization |
check_routes | Check routing DRC |
write_gds -output design.gds | Write GDSII |
write_verilog netlist_final.v | Write final netlist |
write_parasitics -output design.spef | Write SPEF |
write_def -output design.def | Write DEF |